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Novel Access Patterns Based on Overlapping Loading and Processing Times to Reduce Latency and Increase Throughput in Memory-based FFTs
Cita
Kaya, Zeynep 
ORCID: https://orcid.org/0000-0001-9831-6246 and Garrido Gálvez, Mario ORCID: https://orcid.org/0000-0001-5739-3544
(2024).
Novel Access Patterns Based on Overlapping Loading and Processing Times to Reduce Latency and Increase Throughput in Memory-based FFTs.
En: "2024 IEEE 31st Symposium on Computer Arithmetic (ARITH)", 10 - 12 June 2024, Málaga, Spain. ISBN 979-8-3503-8432-1. pp. 52-59.
https://doi.org/10.1109/ARITH61463.2024.00018.
ORCID: https://orcid.org/0000-0001-9831-6246 and Garrido Gálvez, Mario ORCID: https://orcid.org/0000-0001-5739-3544
(2024).
Novel Access Patterns Based on Overlapping Loading and Processing Times to Reduce Latency and Increase Throughput in Memory-based FFTs.
En: "2024 IEEE 31st Symposium on Computer Arithmetic (ARITH)", 10 - 12 June 2024, Málaga, Spain. ISBN 979-8-3503-8432-1. pp. 52-59.
https://doi.org/10.1109/ARITH61463.2024.00018.
Descripción
| Título: | Novel Access Patterns Based on Overlapping Loading and Processing Times to Reduce Latency and Increase Throughput in Memory-based FFTs |
|---|---|
| Autor/es: |
|
| Tipo de Documento: | Ponencia en Congreso o Jornada (Artículo) |
| Título del Evento: | 2024 IEEE 31st Symposium on Computer Arithmetic (ARITH) |
| Fechas del Evento: | 10 - 12 June 2024 |
| Lugar del Evento: | Málaga, Spain |
| Título del Libro: | Proceedings of the IEEE 31st Symposium on Computer Arithmetic |
| Fecha: | Junio 2024 |
| ISBN: | 979-8-3503-8432-1 |
| Materias: | |
| ODS: | |
| Palabras Clave Informales: | Fast Fourier transform (FFT), radix-2, memory-based, low latency, high throughput. |
| Escuela: | E.T.S.I. Telecomunicación (UPM) |
| Departamento: | Ingeniería Electrónica |
| Grupo Investigación UPM: | Laboratorio de Sistemas Integrados LSI |
| Licencias Creative Commons: | Reconocimiento - Sin obra derivada - No comercial |
Resumen
This paper presents novel access patterns for P-parallel N-point radix-2 memory-based fast Fourier transform (FFT) architectures. This work aims to reduce the latency and increase the throughput by changing the data order and/or choosing different places of the architectures to input/output data. In this way, we can eliminate the loading time and/or the time to collect the output data. This results in a reduction in latency and an increase in throughput. Likewise, the architectures use the same permutation circuits for each iteration, which simplifies the circuit. In addition to improvements in latency and throughput with different access patterns for memory-based FFTs, this work also offers bit-reversed or natural input/output alternatives.
Proyectos asociados
Tipo
Código
Acrónimo
Responsable
Título
Gobierno de España
PID2021-126991NA-I00
RAFFTING
Mario Garrido
Sin especificar
Gobierno de España
RYC2018-025384-I
Sin especificar
Sin especificar
Sin especificar
Más información
| ID de Registro: | 87789 |
|---|---|
| Identificador DC: | https://oa.upm.es/87789/ |
| Identificador OAI: | oai:oa.upm.es:87789 |
| URL Portal Científico: | https://portalcientifico.upm.es/es/ipublic/item/10243092 |
| Identificador DOI: | 10.1109/ARITH61463.2024.00018 |
| URL Oficial: | https://ieeexplore.ieee.org/document/10579369 |
| Depositado por: | Dr. Mario Garrido Gálvez |
| Depositado el: | 12 Feb 2025 07:14 |
| Ultima Modificación: | 12 Feb 2025 07:22 |
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