Synthesis of verifiable concurrent Java components from formal models

Mariño Carballo, Julio ORCID: https://orcid.org/0000-0002-2665-7612, Alborodo, Raúl Nestor Neri ORCID: https://orcid.org/0000-0001-7688-1447, Fredlund, Lars-Áke ORCID: https://orcid.org/0000-0002-8296-4609 and Herranz Nieva, Ángel ORCID: https://orcid.org/0000-0002-6433-5681 (2019). Synthesis of verifiable concurrent Java components from formal models. "Software and Systems Modeling", v. 18 (n. 1); pp. 71-105. ISSN 16191366. https://doi.org/10.1007/s10270-017-0581-1.

Descripción

Título: Synthesis of verifiable concurrent Java components from formal models
Autor/es:
Tipo de Documento: Artículo
Título de Revista/Publicación: Software and Systems Modeling
Fecha: 8 Febrero 2019
ISSN: 16191366
Volumen: 18
Número: 1
Materias:
Palabras Clave Informales: Concurrency; CSP; Java; JCSP; JML; Key; Message passing; Model-driven; shared resources; Verification
Escuela: E.T.S. de Ingenieros Informáticos (UPM)
Departamento: Lenguajes y Sistemas Informáticos e Ingeniería del Software
Licencias Creative Commons: Reconocimiento - Sin obra derivada - No comercial

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Resumen

Concurrent systems are hard to program, and ensuring quality by means of traditional testing techniques is often very hard as errors may not show up easily and reproducing them is hard. In previous work, we have advocated a model-driven approach to the analysis and design of concurrent, safety-critical systems. However, to take full advantage of these techniques, they must be supported by code generation schemes for concrete programming languages. Ideally, this translation should be traceable, automated and should support the verification of the generated code. In our work, we consider the problem of generating a concurrent Java component from a high-level model of inter-process interaction (i.e., communication + synchronization). We call our formalism shared resources. From the model, which can be represented in mathematical notation or written as a Java interface annotated using an extension of JML, a Java component can be obtained by a semiautomatic translation. We describe how to obtain shared memory (using a priority monitors library) and message passing (using the JCSP library) implementations. Focusing on inter-process interaction for formal development is justified by several reasons, e.g., mathematical models are language-independent and allow to analyze certain concurrency issues, such as deadlocks or liveness properties prior to code generation. Also, the Java components produced from the shared resource model will contain all the concurrency-related language constructs, which are often responsible for many of the errors in concurrent software. We follow a realistic approach where the translation is semiautomatic (schemata for code generation) and the programmer still retains the power of coding or modifying parts of the code for the resource. The code thus obtained is JML-annotated Java with proof obligations that help with code traceability and verification of safety and liveness properties. As the code thus obtained is not automatically correct, there is still the need to verify its conformance to the original specs. We illustrate the methodology by developing a concurrent control system and verifying the code obtained using the KeY program verification tool. We also show how KeY can be used to find errors resulting from a wrong use of the templates.

Proyectos asociados

Tipo
Código
Acrónimo
Responsable
Título
Comunidad de Madrid
S2013/ICE-2731
Sin especificar
Sin especificar
Sin especificar
Gobierno de España
TIN2012-39391-C04-03
Sin especificar
Sin especificar
Sin especificar

Más información

ID de Registro: 94514
Identificador DC: https://oa.upm.es/94514/
Identificador OAI: oai:oa.upm.es:94514
URL Portal Científico: https://portalcientifico.upm.es/es/ipublic/item/5498256
Identificador DOI: 10.1007/s10270-017-0581-1
URL Oficial: https://link.springer.com/article/10.1007/s10270-0...
Depositado por: iMarina Portal Científico
Depositado el: 28 Feb 2026 18:59
Ultima Modificación: 28 Feb 2026 18:59