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Top-down methodology employing hardware description languages (HDLs) for designing digital control in power converters

Laguna Ruiz, Leonardo and Prieto López, Roberto and Oliver Ramírez, Jesús Angel and Cobos Márquez, José Antonio (2008) Top-down methodology employing hardware description languages (HDLs) for designing digital control in power converters. In: 11th IEEE International Conference on Power Electronics (CIEP 2008), 24/08/2008-27/08/2008, Cuernavaca (México).

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Item Type:Presentation at Congress or Day (Article)
Authors/Creators:
Creators NameCreators email (if known)
Laguna Ruiz, Leonardo
Prieto López, Roberto
Oliver Ramírez, Jesús Angel
Cobos Márquez, José Antonio
Title:Top-down methodology employing hardware description languages (HDLs) for designing digital control in power converters
Event Title:11th IEEE International Conference on Power Electronics (CIEP 2008)
Event Dates:24/08/2008-27/08/2008
Event Location:Cuernavaca (México)
Title of Book:Power Electronics Congress, 2008. CIEP 2008. 11th IEEE International
Publisher:IEEE Computer Society
Date:2008
ISBN:978-1-4244-2718-5
Department:Automation, Electronic Engineering and Industrial Computers
Faculty:E.T.S.I. Industrial (UPM)
Creative Commons licenses:Recognition - No derivative works - No commercial
Item ID:3408
Subjects:Electronics
Computer Science
Education

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Official URL: http://ieeexplore.ieee.org/xpl/mostRecentIssue.jsp?punumber=4648127

Abstract

This paper presents a research line oriented to develop methodologies that takes advantage of hardware description languages in order to simplify the design of power converters that employ digital control techniques. The methodology focuses on setting the adequate communications among subsystems in order to simplify the change of the levels of abstraction of the subsystem’s models (from the conceptual level to the actual electric + synthesizable code). Changing the level of abstraction in the design process pretends: first to provide useful models at early designing steps; second, to optimize the simulation of the system, and at same time optimize the verification step.

Item Type:Presentation at Congress or Day (Article)
Subjects:Electronics
Computer Science
Education
Código ID:3408
Depositado Por:Memoria Investigacion
Depositado el:22 Jun 2010 10:04
Last Modified:22 Jun 2010 10:04

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